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Pedro Reviriego Vasallo
Visiting Professor

Telephone:: (+34) 91-624-6232
Fax: 91-624-8749
E-mail: revirieg@it.uc3m.es
Address: Universidad Carlos III de Madrid. Avda de la Universidad, 30
E-28911 Leganés (Madrid) Spain
Visits: Escuela Politécnica Superior · Building Torres Quevedo ·
Office 4.0.F02



 RESEARCH

I currently work on two exciting topics that are key for modern computing systems. The first one is Approximate and Fault Tolerant Computing that is needed to reduce the cost of processing data and also to ensure that the results are reliable which is a fundamental requirement in many systems for example those that are safety critical. The second is Probabilistic Data Structures that are used to accelerate many common data processing operations reducing the storage and computational effort dramatically.  You can find details of some of my recent publications on both areas at the bottom of the page to get a better idea of my work.  You will see that I work with many people around the world. I believe that combining different profiles and expertise provides a huge benefit for research, especially in areas that involve different topics like the ones I work in. This clearly a case where 2+2 add to more than 4.  In fact, I have an Erdős number of 3. This is interesting as like him, I am a prolific author with many collaborations and a strong believer in working with other researchers to tackle complex problems.

So, let us get to work. There are some specific topics for which I either lack some specific knowledge (for example on the mathematical side or on the low-level circuit implementation) or some technical capabilities (for example programming advanced processors)  and that I have there waiting to be explored. A few Open Problems and Ideas are listed below and to facilitate matching to your expertise, what I am missing is marked in parenthesis.

1.       Cuckoo hashing for multiple size items or duplicated keys (mathematical modeling of cuckoo hashing). In some applications it is beneficial to have entries of different sizes in the same key value tables, for example in high speed switches in other applications, you have entries of the same size but some keys are duplicated with different values. Understanding the impact of supporting duplicates of different size elements on cuckoo hash has so far been done by simulation. Deriving theoretical guarantees is of interest both theoretically and practically as systems are already using them.

2.       Approximate Multi-Level Cell Memories (memory design). Some emerging memory technologies like Phase Change Memories can support multiple levels and thus bits per cell leading to denser designs. However, pushing the number of levels increases the probability of having limited magnitude errors. These errors can be mitigated using error correction codes. In some applications a percentage of errors may be manageable, so the question is how much can we save by pushing the number of levels and the error rates. I can work out the acceptable error rates, but I cannot design the memory cells.

3.       Analysis of Exact Match in One Memory Access (EMOMA) (mathematical modeling of a structure that combines cuckoo hash and counting Bloom filters). In EMOMA, we presented a data structure that using a filter ensures that all exact matches on an external table are done in one memory access. Again, the evaluation was done by simulation and no theoretical analysis was presented. Deriving theoretical guarantees on occupancy is of interest.

4.       Approximate Registers (logic cell design). Approximate operations and memory have been widely studied but the design of approximate registers that are used to store intermediate results and for pipelining in ASICs has not been explored. Can we design approximate flip-flops that reduce area and power at the cost of introducing errors? If so, they can be used in combination with approximate operations for example in multiply and accumulate blocks.

5.       Analysis of cuckoo hashing selectable hash (mathematical modeling of a structure that combines cuckoo hash with a hash selection table). Parallel implementations of cuckoo hashing with a memory per table enable lookups to complete in one memory access cycle but introduce and additional cost due to memory fragmentation (using a single larger memory is cheaper than several smaller ones having in total the same size). A solution is to use a small table to select the hash function. Again, the evaluation was done by simulation and no theoretical analysis was presented. Deriving theoretical guarantees on occupancy is of interest.

6.       Algorithmic Based Error Compensations (cross-layer design). It seems that in some algorithms, the result can be used to estimate the error introduced by approximate operations and thus can be used to compensate it. This would enable the use of cheaper approximate operations and can lead to significantly more efficient implementations. This work requires combining the knowledge of the algorithms and the low level arithmetic operations.

7.       Collisions on the Count-Min Sketch (mathematical modeling of collisions). How many elements do we need to be tested to find a set of elements that collide on all the arrays of a Count-Min Sketch with a target element? This is similar to a coupon’s collector problem but not quite the same. We have derived upper and lower bounds but a better theoretical approximation would be better. This has applications for Count-Min Sketch security.

Have you found any topic that fits your expertise and that is worth exploring? Then you can contact me, and I can give you further details and we may end up working together. Even if we do not, I would be glad to see those topics moving forward. Conversely, if you have ideas on these areas and you need help with some specific aspect, I will also be happy to discuss.

 

Recent Publications

1.       P. Reviriego, J. Martinez, O. Rottenstreich, S. Liu and F. Lombardi, “Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog,” in IEEE Transactions on Dependable and Secure Computing (in press).

2.       P. Reviriego, J. A. Martinez and M. Ottavi, "Soft Error Tolerant Count Min Sketches," in IEEE Transactions on Computers (in press) doi: 10.1109/TC.2020.2987890

3.       P. Reviriego and D. Larrabeiti, "Denial of Service Attack on Cuckoo Filter Based Networking Systems," in IEEE Communications Letters, vol. 24, no. 7, pp. 1428-1432, July 2020. doi: 10.1109/LCOMM.2020.2983405

4.       P. Reviriego and D. Ting, "Security of HyperLogLog (HLL) Cardinality Estimation: Vulnerabilities and Protection," in IEEE Communications Letters, vol. 24, no. 5, pp. 976-980, May 2020. doi: 10.1109/LCOMM.2020.2972895

5.       S. Liu, P. Reviriego and F. Lombardi, "Codes for Limited Magnitude Error Correction in Multilevel Cell Memories," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp. 1615-1626, May 2020. doi: 10.1109/TCSI.2019.2961847

6.       M. Mitzenmacher, S. Pontarelli, and P. Reviriego, “Adaptive Cuckoo Filters”, in ACM Journal of Experimental Algorithmics vol. 25, 1, Article 1.1, April 2020.  doi:https://doi.org/10.1145/3339504

7.       P. Reviriego, J. Martínez and S. Pontarelli, "Improving Packet Flow Counting with Fingerprint Counting," in IEEE Communications Letters, vol. 24, no. 1, pp. 76-80, Jan. 2020. doi: 10.1109/LCOMM.2019.2953907

8.       S. Liu, P. Reviriego, J. A. Hernández and F. Lombardi, "Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning," in IEEE Transactions on Emerging Topics in Computing (in press). doi: 10.1109/TETC.2019.2963268

9.       S. Liu, P. Reviriego, J. Guo, J. Han and F. Lombardi, "Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design," in IEEE Transactions on Emerging Topics in Computing (in press). doi: 10.1109/TETC.2019.2960491

10.   J. Li, P. Reviriego, L. y. Xiao and H. Wu, "Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes," in IEEE Transactions on Emerging Topics in Computing (in press). doi: 10.1109/TETC.2019.2953139

11.   P. Reviriego and O. Rottenstreich, "The Tandem Counting Bloom Filter - It Takes Two Counters to Tango," in IEEE/ACM Transactions on Networking, vol. 27, no. 6, pp. 2252-2265, Dec. 2019. doi: 10.1109/TNET.2019.2944954

12.   S. Liu, K. Chen, P. Reviriego, W. Liu, A. Louri and F. Lombardi, "Reduced Precision Redundancy for Reliable Processing of Data," in IEEE Transactions on Emerging Topics in Computing (in press). doi: 10.1109/TETC.2019.2947617

13.   P. Reviriego, J. Martínez and S. Pontarelli, "CFBF: Reducing the Insertion Time of Cuckoo Filters With an Integrated Bloom Filter," in IEEE Communications Letters, vol. 23, no. 10, pp. 1857-1861, Oct. 2019. doi: 10.1109/LCOMM.2019.2930508

14.   S. Liu, P. Reviriego and F. Lombardi, "Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP)," in IEEE Transactions on Emerging Topics in Computing (in press) doi: 10.1109/TETC.2019.2922631

15.   Ramos, R. G. Toral, P. Reviriego and J. A. Maestro, "An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs," in IEEE Transactions on Computers, vol. 68, no. 9, pp. 1404-1410, 1 Sept. 2019. doi: 10.1109/TC.2019.2907238

16.   P. Reviriego, S. Liu, O. Rottenstreich and F. Lombardi, "Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes," in IEEE Transactions on Computers, vol. 68, no. 5, pp. 798-803, 1 May 2019. doi: 10.1109/TC.2018.2890651

17.   K. Chen, L. Chen, P. Reviriego and F. Lombardi, "Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC)," in IEEE Transactions on Computers, vol. 68, no. 5, pp. 784-790, 1 May 2019. doi: 10.1109/TC.2018.2885044

18.   P. Reviriego, S. Pontarelli and A. Ullah, "Error Detection and Correction in SRAM Emulated TCAMs," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 2, pp. 486-490, Feb. 2019. doi: 10.1109/TVLSI.2018.2877131

19.   Sánchez-Macián, L. A. Aranda, P. Reviriego, V. Kiani and J. A. Maestro, "Enhancing Instruction TLB Resilience to Soft Errors," in IEEE Transactions on Computers, vol. 68, no. 2, pp. 214-224, 1 Feb. 2019. doi: 10.1109/TC.2018.2874467

20.   S. Pontarelli, P. Reviriego and M. Mitzenmacher, "EMOMA: Exact Match in One Memory Access," in IEEE Transactions on Knowledge and Data Engineering, vol. 30, no. 11, pp. 2120-2133, 1 Nov. 2018. doi: 10.1109/TKDE.2018.2818716

21.   R. González-Toral, P. Reviriego, J. A. Maestro and Z. Gao, "A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs," in IEEE Transactions on Computers, vol. 67, no. 7, pp. 1039-1045, 1 July 2018. doi: 10.1109/TC.2018.2792445

22.   R. González-Toral, S. Liu, P. Reviriego and J. A. Maestro, "Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 4, pp. 1293-1302, April 2018. doi: 10.1109/TCSI.2017.2743248

23.   A. Ramos, A. Ullah, P. Reviriego and J. A. Maestro, "Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs," in IEEE Transactions on Computers, vol. 67, no. 2, pp. 299-304, 1 Feb. 2018. doi: 10.1109/TC.2017.2737996

 


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